25 lines
780 B
Verilog
25 lines
780 B
Verilog
module pathlib
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// import incubaid.herolib.core.smartid
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// // sids_acknowledge .
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// // means our redis server knows about the sid's found, so we know which ones to generate new
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// pub fn (mut path Path) sids_acknowledge(cid smartid.CID) ! {
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// t := path.read()!
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// cid.sids_acknowledge(t)!
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// }
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// // sids_replace .
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// // find parts of text in form sid:*** till sid:****** .
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// // replace all occurrences with new sid's which are unique .
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// // cid = is the circle id for which we find the id's .
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// // sids will be replaced in the files if they are different
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// pub fn (mut path Path) sids_replace(cid smartid.CID) ! {
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// t := path.read()!
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// t2 := cid.sids_replace(t)!
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// if t2 != t {
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// // means we have change and we need to write it
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// path.write(t2)!
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// }
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// }
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