35 lines
1.2 KiB
Verilog
35 lines
1.2 KiB
Verilog
module docusaurus
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// fn (mut site DocSite) process_md(mut path pathlib.Path, args ImportSource) ! {
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// if path.is_dir() {
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// mut pathlist_images := path.list(
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// regex: [r'.*\.png$', r'.*\.jpg$', r'.*\.svg$', r'.*\.jpeg$']
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// recursive: true
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// )!
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// for mut mypatho_img in pathlist_images.paths {
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// // now copy the image to the dest
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// dest := '${site.path_build.path}/docs/${args.dest}/img/${texttools.name_fix(mypatho_img.name())}'
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// // println("image copy: ${dest}")
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// mypatho_img.copy(dest: dest, rsync: false)!
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// }
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// mut pathlist := path.list(regex: [r'.*\.md$'], recursive: true)!
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// for mut mypatho2 in pathlist.paths {
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// site.process_md(mut mypatho2, args)!
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// }
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// return
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// }
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// mydest := '${site.path_build.path}/docs/${args.dest}/${texttools.name_fix(path.name())}'
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// mut mydesto := pathlib.get_file(path: mydest, create: true)!
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// mut mymd := markdownparser.new(path: path.path)!
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// mut myfm := mymd.frontmatter2()!
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// if !args.visible {
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// myfm.args['draft'] = 'true'
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// }
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// // println(myfm)
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// // println(mymd.markdown()!)
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// mydesto.write(mymd.markdown()!)!
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// // Note: exit(0) was removed to prevent unexpected program termination
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// }
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